HD6417727BP160CV Datasheet, PDF (923/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 28 A/D Converter
Bit 5—Scan Mode (SCN): Selects multi mode or scan mode when the MULTI bit is set to 1. See
the description of bit 4 in section 28.2.2, A/D Control/Status Register (ADCSR).
Bits 4 and 3—Reserved (RESVD1, RESVD2): These bits always read 0. The write value should
always be 0.
Bits 2 to 0—Resrved: These bits are always read as 0. The write value should always be 0.
28.3 Bus Master Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8
bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly
by the bus master, the lower byte is read through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the bus master and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the bus master.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed.
Figure 28.2 shows the data flow for access to an A/D data register.
See section 28.7.3, Access Size and Read Data.
Rev.6.00 Mar. 27, 2009 Page 865 of 1036
REJ09B0254-0600