HD6417727BP160CV Datasheet, PDF (267/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 8 User Break Controller
8.2.4 Break Address Register B (BARB)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB BAB
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in
channel B. Control bits XYE and XYS in the BBRB selects an address bus for break condition B.
If the XYE is 0, then BARB specifies the break address on logic or internal bus, LAB or IAB. If
the XYE is 1, then the BAB31 to 16 specifies the break address on XAB (bits 15 to 1) and the
BAB15 to 0 specifies the break address on YAB (bits 15 to 1). However, you have to choose one
of two address buses for the break. A power-on reset initializes BARB to H'00000000.
XYE = 0
XYE = 1
BAB31 to 16
L(I) AB31 to 16
XAB15 to 1 (XYS = 0)
BAB15 to 0
L(I) AB15 to 0
YAB15 to 1 (XYS = 1)
Rev.6.00 Mar. 27, 2009 Page 209 of 1036
REJ09B0254-0600