HD6417727BP160CV Datasheet, PDF (667/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
Bit 12: REDG
Description
0
Sample RXD_SIO by falling edge of SCK_SIO
1
Sample RXD_SIO by rising edge of SCK_SIO
Note: This mode is effective in master mode 1 or master mode 2.
(Initial value)
Bits 11 to 8—Frame Length (FL3 to FL0)
Bit 11: Bit 10: Bit 9: Bit 8:
FL3
FL2
FL1
FL0
Description
0
0
0/1* 0/1* Slot size is 8 bit, frame length is 8 bit
(Initial value)
1
0
0
Slot size is 8 bit, frame length is 16 bit
1
Slot size is 8 bit, frame length is 32 bit
1
0
Slot size is 8 bit, frame length is 64 bit
1
Slot size is 8 bit, frame length is 128 bit
1
0
0/1* 0/1* Slot size is 16 bit, frame length is 16 bit
1
0
0
Slot size is 16 bit, frame length is 32 bit
1
Slot size is 16 bit, frame length is 64 bit
1
0
Slot size is 16 bit, frame length is 128 bit
1
Slot size is 16 bit, frame length is 256 bit
Notes: 1. When 8 bit slot size is chosen, control data is not able to be transmitted or received.
2. When LSB first is chosen, control data is not able to be transmitted or received.
* Same setting in both 1 and 0. (Don’t care)
Bit 7—Hi-Z Output Control under Ineffective Case for Transmission (TXDIZ): Ineffective
case is the case of transmit data or command are not assigned or transmit operation is disabled.
Bit 7: TXDIZ
0
1
Description
1 output ineffective transmission
Hi-Z output ineffective transmission
(Initial value)
Bit 6—LSB First Transmission and Reception (LSBF): Selects MSB first or LSB first for the
transmission or reception frame.
Bit 6: LSBF
0
1
Description
MSB First
LSB First
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 609 of 1036
REJ09B0254-0600