HD6417727BP160CV Datasheet, PDF (715/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
Section 21 Analog Front End Interface (AFEIF)
21.1 Overview
This LSI has an AFE interface that supports softwaremodem. This AFE interface can efficiently
execute the modem processing, because it includes 128 stages of FIFO for each of transmission
and reception. This AFE interface also includes the interface to data access arrangement (DAA)
such as dial pulse generator circuit and ringing detection. Therefore, it is possible to establish a
modem system with a minimum of hardware.
21.1.1 Features
• Serial interface with FIFO
• Clock synchronized serial interface
• Transmit/receive FIFO size is 16 bits (maximum) × 128 words
• Transmit/receive interrupt threshold size is programmable
• Dial pulse generator circuit is included
• Ringing detection (calling signal) function is included
Rev.6.00 Mar. 27, 2009 Page 657 of 1036
REJ09B0254-0600