HD6417727BP160CV Datasheet, PDF (86/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 2 CPU
three-step instruction. When RF[1:0] = 10, it means the current repeat module consists of four or
more instructions.
Although RC[11:0] and RF[1:0] can be changed by a store/load to SR, use of the dedicated
manipulation instruction SETRC is recommended.
The SR also has a 12-bit repeat counter RC which is used for efficient loop control. Repeat start
register (RS) and repeat end register (RE) are also introduced for the loop control. They keep the
start and end addresses of a loop (the contents of the registers, RS and RE are slightly different
from the actual loop start and end address).
Modulo register, MOD is introduced to realize modulo addressing for circular data buffering.
MOD keeps the modulo start address (MS) and the modulo end address (ME).
In order to access RS, RE and MOD, load/store (control register) instructions for them are
introduced. An example for RS is as follows:
LDC Rm,RS;
LDC.L @Rm+,RS;
STC RS,Rn;
STC.L RS,@-Rn;
Rm → RS
(Rm) → RS, Rm+4 → Rm
RS → Rn
Rn-4 → Rn, RS → (Rn)
Address set instructions for the RS and RE are also prepared.
LDRS @(disp,PC); disp × 2 + PC → RS
LDRE @(disp,PC); disp × 2 + PC → RE
Rev.6.00 Mar. 27, 2009 Page 28 of 1036
REJ09B0254-0600