HD6417727BP160CV Datasheet, PDF (799/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 24 USB HOST Module
24.2.9 HcControlHeadED
HcControlHeadED (H'04000420)
The HcControlHeadED register includes a physical address of first ED.
Register: HcControlHeadED
Bits
Reset R/W
31–4
0h
R/W
3–0
0h
—
Offset: 20–23
Description
ControlHeadED (CHED)
Pointer to the Control List Head ED. (Within SRAM memory
space)
Reserved.
24.2.10 HcControlCurrentED
HcControlCurrentED Regsiter (H'04000424)
The HcControlCurrentED register includes a physical address of current ED.
Register: HcControlCurrentED Offset: 24–27
Bits
Reset R/W
Description
31–4
0h
R/W
ControlCurrentED (CCED)
Pointer to the current Control List ED. (Within memory area3)
3–0
0h
—
Reserved.
24.2.11 HcBulkHeadED
HcBulkHeadED Register (H'04000428)
The HcBulkHeadEDregister includes a physical address of first ED in Bulk List.
Register: HcBulkHeadED
Bits
Reset R/W
31–4
0h
R/W
3–0
0h
—
Offset: 28–2B
Description
BulkHeadED (BHED)
Pointer to the Bulk List Head ED. (Within memory area3)
Reserved.
Rev.6.00 Mar. 27, 2009 Page 741 of 1036
REJ09B0254-0600