HD6417727BP160CV Datasheet, PDF (1033/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 32 Electrical Characteristics
32.3.8 Peripheral Module Signal Timing
Table 32.11 Peripheral Module Signal Timing
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Module Item
Symbol Min
Max
RTC
Oscillation settling time
t_ROSC
—
3
SCI
Input clock Asynchronization
t_SCYC
4
—
cycle
Clock synchronization
6
—
Input clock rise time
Input clock fall time
Input clock pulse width
Transmission data delay time
Receive data setup time
(clock synchronization)
t_SCKR
—
1.5
t_SCKF
—
1.5
t_SCKW
0.4
0.6
t_TXD
—
100
t_RXS
100
—
Receive data hold time
(clock synchronization)
RTS delay time
CTS setup time
(clock synchronization)
CTS hold time
(clock synchronization)
t_RXH
100
—
t_RTSD
—
100
t_CTSS
100
—
t_CTSH
100
—
Port
Output data delay time
t_PORTD
Input data setup time (1)
t_PORTS1
Input data hold time (1)
t_PORTH1
Input data setup time (2)
t_PORTS2
Input data hold time (2)
t_PORTH2
Input data setup time (3)
t_PORTS3
DMAC
Input data hold time (3)
DREQ setup time
DREQ hold time
t_PORTH3
t_DRQS
t_DREQH
DRAK delay time
t_DRAKD
Note: * P_cyc stands for “peripheral clock (Pφ) cycle.”
—
26
15
—
8
—
t_cyc + 15 —
8
—
3 t_cyc + 15 —
8
—
8
—
8
—
—
14
Unit Figure
s
32.41
P_cyc* 32.42
32.43
P_cyc* 32.42
t_Scyc
ns 32.43
ns 32.44
ns 32.45
32.46
Rev.6.00 Mar. 27, 2009 Page 975 of 1036
REJ09B0254-0600