HD6417727BP160CV Datasheet, PDF (349/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Area 0: H'00000000
Area 1: H'04000000
Area 2: H'08000000
Area 3: H'0C000000
Area 4: H'10000000
Area 5: H'14000000
Area 6: H'18000000
Ordinary memory/
burst ROM
Internal I/O
Ordinary memory/
synchronous DRAM
Ordinary memory/
synchronous DRAM
Ordinary memory
Ordinary memory/
burst ROM/PCMCIA
Ordinary memory/
burst ROM/PCMCIA
The PCMCIA interface is shared
by the memory and I/O card
The PCMCIA interface is shared
by the memory and I/O card
Figure 12.3 Physical Space Allocation
Memory Bus Width: The memory bus width in this LSI can be set for each area. In area 0, an
external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on
reset as setting of MD4 and MD3 as below table .
Table 12.4 Correspondence between External Pins (MD4 and MD3) and Memory bus
width in area0
MD4
0
1
MD3
0
1
0
1
Memory Size
Reserved (Setting prohibited)
8 bits
16 bits
32 bits
For areas 2 to 6, byte, word, and longword may be chosen for the bus width using bus control
register 2 (BCR2) whenever ordinary memory, ROM, or burst ROM are used.
When the PCMCIA interface is used, set the bus width to byte or word. When synchronous
DRAM is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. When
using the port function, set each of the bus widths to byte or word for all areas. For more
information, see section 12.2.2, Bus Control Register 2 (BCR2).
Rev.6.00 Mar. 27, 2009 Page 291 of 1036
REJ09B0254-0600