HD6417727BP160CV Datasheet, PDF (123/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 2 CPU
Table 2.19 CPU Instruction Types
Type
Kinds of
Instruction Op Code
Data transfer 5
instructions
MOV
Arithmetic 21
operation
instructions
MOVA
MOVT
SWAP
XTRCT
ADD
ADDC
ADDV
CMP/cond
DIV1
DIV0S
DIV0U
DMULS
DMULU
DT
EXTS
EXTU
MAC
MUL
MULS
MULU
NEG
NEGC
SUB
SUBC
SUBV
Function
Number of
Instructions
Data transfer
39
Immediate data transfer
Peripheral module data transfer
Structure data transfer
Effective address transfer
T bit transfer
Upper/lower swap
Extraction of middle of linked registers
Binary addition
33
Binary addition with carry
Binary addition with overflow check
Comparison
Division
Signed division initialization
Unsigned division initialization
Signed double-precision multiplication
Unsigned double-precision multiplication
Decrement and test
Sign extension
Zero extension
Multiply-and-accumulate, double-
precision multiply-and-accumulate
Double-precision multiplication
(32 × 32 bits)
Signed multiplication (16 × 16 bits)
Unsigned multiplication (16 × 16 bits)
Sign inversion
Sign inversion with borrow
Binary subtraction
Binary subtraction with carry
Binary subtraction with underflow
Rev.6.00 Mar. 27, 2009 Page 65 of 1036
REJ09B0254-0600