HD6417727BP160CV Datasheet, PDF (262/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 8 User Break Controller
• Maximum repeat times for the break condition: 2¹² – 1 times. (It is only for channel B)
• Eight pairs of branch source/destination buffers.
8.1.2 Block Diagram
Figure 8.1 is a block diagram of the UBC.
Access
Control
XAB/YAB
IAB LAB
Access
comparator
Address
comparator
ASID
comparator
Channel A
BBRA
BARA
BAMRA
BASRA
MDB
Access
comparator
Address
comparator
ASID
comparator
Data
comparator
Channel B
PC Trace
CONTROL
BBRB
BARB
BAMRB
BASRB
BDRB
BDMRB
BETR
BRSR
BRDR
BRCR
LDB/IDB/
XDB/YDB
CPU state
signals
Legend
BBRA:
BARA:
BAMRA:
BASRA:
BBRB:
BARB:
BAMRB:
Break bus cycle register A
Break address register A
Break address mask register A
Break ASID register A
Break bus cycle register B
Break address register B
Break address mask register B
User break request
UBC Location
CCN Location
BASRB:
BDRB:
BDMRB:
BETR:
BRSR:
BRDR:
BRCR:
Break ASID register B
Break data register B
Break data mask register B
Break execution times register
Branch source register
Branch destination register
Break control register
Figure 8.1 Block Diagram of User Break Controller
Rev.6.00 Mar. 27, 2009 Page 204 of 1036
REJ09B0254-0600