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HD6417727BP160CV Datasheet, PDF (637/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series
Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 1—Receive FIFO Data Full (RDF): Indicates that received data is transferred to the receive
FIFO data register 2 (SCFRDR2), the quantity of data in SCFRDR2 becomes more than the
number of receive triggers specified by the RTRG1 and RTRG0 bits in FIFO control register 2
(SCFCR2).
Bit 1: RDF
Description
0
The quantity of transmit data written to SCFRDR2 is less than the specified
number of receive triggers.
(Initial value)
RDF is cleared to 0 at power-on reset or in standby mode, or when SCFRDR2 is
read until the quantity of receive data in SCFRDR2 is less than the specified
receive trigger number, and software reads 1 from RDF and then writes 0 to
RDF.
1
The quantity of receive data in SCFRDR2 is more than the specified number of
receive triggers.
RDF is set to 1 when the quantity of receive data which is greater than the
specified number of receive triggers is stored in SCFRDR2.*
Note: * Since SCFTDR2 is a 16-byte FIFO register, the maximum quantity of data which can be
read when RDF is 1 is the specified number of receive triggers. If attempted to read after
all data in the SCFRDR2 have been read, the data is undefined. The quantity of receive
data in SCFRDR2 is indicated by the lower 8 bits of SCFTDR2.
Bit 0—Receive Data Ready (DR): Indicates that the receive FIFO data register 2 (SCFRDR2)
stores the data which is less than the specified number of receive triggers, and that next data is not
yet received after 15 ETU has elapsed from the last stop bit.
Bit 0: DR
Description
0
Receive is in progress, or no received data remains in SCFRDR2 after
completing receive normally.
(Initial value)
DR is cleared to 0 when the chip is power-on reset or enters standby mode, or
software reads DR after it has been set to 1, then writes 0 in DR.
1
Next receive data is not received.
DR is set to 1 when SCFRDR2 stores the data which is less than the specified
number of receive triggers, and that next data is not yet received after 15 ETU
has elapsed from the last stop bit.*
Note: * This is equivalent to 1.5 frames with the 8-bit 1-stop-bit format. (ETU: Element Time Unit)
Rev.6.00 Mar. 27, 2009 Page 579 of 1036
REJ09B0254-0600