HD6417727BP160CV Datasheet, PDF (277/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 8 User Break Controller
8.2.11 Branch Source Register (BRSR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SVF PID2 PID1 PID0 BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA
27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA BSA
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: R R R R R R R R R R R R R R R R
Note: * Undefined
BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer
(3 bits) which indicates the number of cycles from fetch to execution for the last executed
instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0,
when BRSR is read and also initialized by power-on resets or manual resets. Other bits are not
initialized by reset. Eight BRSR registers have queue structure and a stored register is shifted
every branch.
Bit 31—BRSR Valid Flag (SVF): Indicates whether the address and the pointer by which the
branch source address can be calculated. When a branch source address is fetched, this flag is set
to 1. This flag is cleared to 0 in reading BRSR.
Bit 31: SVF
0
1
Description
The value of BRSR register is invalid
The value of BRSR register is valid
Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0 to
7). These bits indicate the instruction buffer number which stores the last executed instruction
before branch.
Bits 30 to 28:
PID
Even
Odd
Description
PID indicates the instruction buffer number.
PiD+2 indicates the instruction buffer number
Rev.6.00 Mar. 27, 2009 Page 219 of 1036
REJ09B0254-0600