HD6417727BP160CV Datasheet, PDF (681/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
This bit is effective when 1 is written to RXE bit of SICTR register. This bit is cleared when 1 is
written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this
bit.
Bit 2: TFUDR
0
1
Description
Transmit FIFO under run does not occur
Transmit FIFO under run occurs
(Initial value)
Bit 1—Receive FIFO Under Run (RFUDR): Receive FIFO under run shows that SIRDR
register is read when receive FIFO is empty.
The data that has been read out from SIRDR is not guaranteed when this under run has occurred.
This bit is effective when 1 is written to RXE bit of SICTR register. This bit is cleared when 1 is
written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is allowed to this
bit.
Bit 1: RFUDR
0
1
Description
Receive FIFO under run does not occur
Receive FIFO under run occurs
(Initial value)
Bit 0—Receive FIFO Over Run (RFOVR): Receive FIFO over shows write action has occurred
to receive FIFO by SIOF, when receive FIFO is full. The received data disappears when receive
FIFO overrun occurs.
This bit is effective when 1 is written to TXE bit or RXE bit of SICTR register. This bit is cleared
when 1 is written to this bit. SIOF issues the transmit interrupt when the interrupt issuing is
allowed to this bit.
Bit 0: RFOVR
0
1
Description
Transmit over run does not generate
Transmit over run generate
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 623 of 1036
REJ09B0254-0600