HD6417727BP160CV Datasheet, PDF (789/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Register: HcControl
Bits
Reset R/W
3
0b
R/W
2
0b
R/W
1, 0
00b
R/W
Section 24 USB HOST Module
Offset: 04–07
Description
IsochronousEnable (IE)
This bit is used by HCD to enable/disable the processing of
isochronous ED. While processing the periodic list, HC will
check the status of this bit when it finds an isochronous ED (F
=1). If set (enabled), the host controller continues to process
ED. If cleared (disabled), the host controller stops the
processing of the periodic list (currently includes only
isochronous ED) and starts to process the bulk/control list.
Setting this bit is guaranteed to be valid in the next frame (not in
the current frame).
0: Processes ED. (initial value)
1: Processes the bulk/control list.
PeriodicListEnable (PLE)
This bit is set to enable the processing of the periodic list. If
cleared by HCD, no periodic list processing is carried out after
next SOF. HC must check this bit before HC starts to process
the list.
0: The periodic list processing is not carried out after next SOF.
(initial value)
1: The periodic list processing is carried out after next SOF.
ControlBulkServiceRatio (CBSR)
This bit specifies the service ration of the control and bulk ED.
The host controller must compare the ratio specified by the
internal calculation whether it has processed several non-
vacant control ED in determining whether another control ED is
continued to be supplied or switched to bulk ED before any a
periodic list is processed. In case of reset, HCD is responsible
for restoring this value.
00: 1:1 (initial value)
01: 2:1
10: 3:1
11: 4:1
Rev.6.00 Mar. 27, 2009 Page 731 of 1036
REJ09B0254-0600