HD6417727BP160CV Datasheet, PDF (633/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 5—Transmit Enable (TE): Enables or disables the SCIF serial transmitter.
Bit 5: TE
Description
0
Transmitter disabled.
(Initial value)
1
Transmitter enabled. *
Note: * Serial transmission starts after writing of transmit data into the SCFTDR2. Select the
transmit format in the SCSMR2 and SCFCR2 and reset the SCFTDR2 before setting TE to
1.
Bit 4—Receive Enable (RE): Enables or disables the SCIF serial receiver.
Bit 4: RE
Description
0
Receiver disabled.^*1
1
Receiver enabled.^*2
(Initial value)
Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, FER, and PER).
These flags retain their previous values.
2. Serial reception starts when a start bit is detected. Select the receive format in the
SCSMR2 before setting RE to 1.
Bits 3 and 2—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1 and CKE0): These bits should always be set to 00.
Rev.6.00 Mar. 27, 2009 Page 575 of 1036
REJ09B0254-0600