HD6417727BP160CV Datasheet, PDF (383/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
is determined within a range of 2 to 11 (2 to 39 for the PCMCIA interface) according to the
number of waits. The setup and hold times of address/CS6 for the read/write strobe signals can be
set in the range 0.5 to 7.5 cycles using A6TED2 to A6TED0 and A6TEH2 to A6TEH0 bits of the
PCR register. (Single-cycle units)
12.3.3 Basic Interface
Basic Timing: The basic interface of this LSI uses strobe signal output in consideration of the fact
that mainly static RAM will be directly connected. Figure 12.5 shows the basic timing of normal
space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for
one cycle to indicate the start of a bus cycle. The CSn signal is negated on the T2 clock falling
edge to secure the negation period. Therefore, in case of access at minimum pitch, there is a half-
cycle negation period.
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WE
signal for the byte to be written is asserted. For details, see section 12.3.1, Endian/Access Size and
Data Alignment.
Read/write for cache fill or write-back follows the set bus width and transfers a total of 16 bytes
continuously. The bus is not released during this transfer. For cache misses that occur during byte
or word operand accesses or branching to odd word boundaries, the fill is always performed by
longword accesses on the chip-external interface. Write-through-area write access and non-
cacheable read/write access are based on the actual address size.
Rev.6.00 Mar. 27, 2009 Page 325 of 1036
REJ09B0254-0600