HD6417727BP160CV Datasheet, PDF (546/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 17 Serial Communication Interface (SCI)
17.2.3 Transmit Shift Register (SCTSR)
Bit:
7
6
5
4
3
2
1
0
R/W:
—
—
—
—
—
—
—
—
The transmit shift register (SCTSR) transmits serial data.
The SCI loads transmit data from the transmit data register (SCTDR) into the SCTSR, then
transmits the data serially from the TxD0 pin, LSB (bit 0) first.
After transmitting one-byte data, the SCI automatically loads the next transmit data from the
SCTDR into the SCTSR and starts transmitting again. If the TDRE bit of the SCSSR is 1,
however, the SCI does not load the SCTDR contents into the SCTSR.
The CPU cannot read or write the SCTSR directly.
17.2.4 Transmit Data Register (SCTDR)
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The transmit data register (SCTDR) is an eight-bit register that stores data for serial transmission.
When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data
written in the SCTDR into the SCTSR and starts serial transmission. Continuous serial
transmission is possible by writing the next transmit data in the SCTDR during serial transmission
from the SCTSR.
The CPU can always read and write the SCTDR. The SCTDR is initialized to H'FF by a reset or in
standby and module standby modes.
Rev.6.00 Mar. 27, 2009 Page 488 of 1036
REJ09B0254-0600