HD6417727BP160CV Datasheet, PDF (331/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 10 On-Chip Oscillation Circuits
10.7.2 Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit read/write register composed of
bits to select the clock used for the count, bits to select the timer mode, and overflow flags. The
WTCSR differs from other registers in that it is more difficult to write to. See section 10.7.3,
Notes on Register Access, for details. Its address is H'FFFFFF86. The WTCSR register is
initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT overflow
causes an internal reset, the WTCSR retains its value. When used to count the clock settling time
for canceling a standby, it retains its value after counter overflow. Use a word access to write to
the WTCSR counter, with H'A5 in the upper byte. Use a byte access to read WTCSR.
Bit:
Initial value:
R/W:
7
TME
0
R/W
6
WT/IT
0
R/W
5
RSTS
0
R/W
4
WOVF
0
R/W
3
IOVF
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Bit 7—Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the
WDT in standby mode or when changing the clock frequency.
Bit 7: TME
0
1
Description
Timer disabled: Count-up stops and WTCNT value is retained
Timer enabled
(Initial value)
Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or an
interval timer.
Bit 6: WT/IT
Description
0
Use as interval timer
(Initial value)
1
Use as watchdog timer
Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly.
Bit 5—Reset Select (RSTS): Selects the type of reset when the WTCNT overflows in watchdog
timer mode. In interval timer mode, this setting is ignored.
Bit 5: RSTS
0
1
Description
Power-on reset
Manual reset
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 273 of 1036
REJ09B0254-0600