HD6417727BP160CV Datasheet, PDF (344/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
12.1.3 Pin Configuration
Table 12.1 lists the BSC pin configuration.
Table 12.1 Pin Configuration
Pin Name
Address bus
Data bus
Bus cycle start
Signal
A25–A0
D15–D0
D31–D16
BS
I/O
Output
I/O
I/O
Output
Chip select 0, 2–4
CS0, CS2–CS4 Output
Chip select 5, 6
CS5/CE1A,
CS6/CE1B
Output
PCMCIA card select
Read/write
CE2A, CE2B
RD/WR
Output
Output
Row address strobe
RAS
Output
Column address strobe CAS
Output
Data enable 0
WE0/DQMLL Output
Data enable 1
WE1/DQMLU/ Output
WE
Data enable 2
WE2/DQMUL/ Output
ICIORD
Description
Address output
Data I/O
When 32-bit bus width, data I/O
Shows start of bus cycle. During burst
transfers, asserts every data cycle.
Chip select signal to indicate area being
accessed.
Chip select signal to indicate area being
accessed. CS5/CE1A and CS6/CE1B can
also be used as CE1A and CE1B of
PCMCIA.
When PCMCIA is used, CE2A and CE2B
Data bus direction indicator signal.
PCMCIA write indicator signal.
When synchronous DRAM is used, RAS
signal.
When synchronous DRAM is used, CAS
signal.
When memory other than synchronous
DRAM is used, selects D7 to D0 write
strobe signal. When synchronous DRAM is
used, selects D7 to D0.
When memory other than synchronous
DRAM and PCMCIA is used, selects D15
to D8 write strobe signal. When
synchronous DRAM is used, selects D15 to
D8. When PCMCIA is used, strobe signal
that indicates the write cycle.
When memory other than synchronous
DRAM and PCMCIA is used, selects D23
to D16 write strobe signal. When
synchronous DRAM is used, selects D23 to
D16. When PCMCIA is used, strobe signal
indicating I/O read.
Rev.6.00 Mar. 27, 2009 Page 286 of 1036
REJ09B0254-0600