HD6417727BP160CV Datasheet, PDF (422/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
12.3.9 Bus Pull-Up
With this LSI, address pin pull-up can be performed when the bus is released by setting the PULA
bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after BACK is asserted.
Figure 12.34 shows the address pin pull-up timing. Similarly, data pin pull-up can be performed
by setting the PULD bit in BCR1 to 1. The data pins should be pulled up when the data bus is not
in use. The data pin pull-up timing for a read cycle is shown in figure 12.35, and the timing for a
write cycle in figure 12.36.
CKIO
A25 to A0
BACK
Pull-up
Hi-Z
Figure 12.34 Pins A25 to A0 Pull-Up Timing
CKIO
D31 to D0
Pull-up
RD
CSn
Pull-up
Figure 12.35 Pins D31 to D0 Pull-Up Timing (Read Cycle)
Rev.6.00 Mar. 27, 2009 Page 364 of 1036
REJ09B0254-0600