HD6417727BP160CV Datasheet, PDF (754/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 23 USB Function Controller
Bit:
7
BRST
Initial value:
0
R/W: R/W
6
EP1
FULL
0
R
5
4
3
2
EP2
EP2 SETUP EP0o
TR EMPTY TS
TS
0
1
0
0
R/W
R
R/W
R/W
1
EP0i
TR
0
R/W
0
EP0i
TS
0
R/W
Bit 7—Bus Reset (BRST): Set to 1 when the bus reset signal is detected on the USB bus.
Bit 6—EP1 FIFO Full (EP1 FULL): This bit is set when endpoint 1 receives one packet of data
normally from the host, and holds a value of 1 as long as there is valid data in the FIFO buffer.
EP1 FULL is a status bit, and cannot be cleared.
Bit 5—EP2 Transfer Request (EP2 TR): This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 2 is received from the host. A NACK handshake is
returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
Bit 4—EP2 FIFO Empty (EP2 EMPTY): This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be written. EP2 EMPTY is a status bit, and
cannot be cleared.
Bit 3—Setup Command Receive Complete (SETUP TS): This bit is set to 1 when endpoint 0
receives normally a setup command requiring decoding on the application side, and returns an
ACK handshake to the host.
Bit 2—EP0o Receive Complete (EP0o TS): This bit is set to 1 when endpoint 0 receives data
from the host normally, stores the data in the FIFO buffer, and returns an ACK handshake to the
host.
Bit 1—EP0i Transfer Request (EP0i TR): This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 0 is received from the host. A NACK handshake is
returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
Bit 0—EP0i Transmit Complete (EP0i TS): This bit is set when data is transmitted to the host
from endpoint 0 and an ACK handshake is returned.
Rev.6.00 Mar. 27, 2009 Page 696 of 1036
REJ09B0254-0600