HD6417727BP160CV Datasheet, PDF (630/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.5 Serial Mode Register 2 (SCSMR2)
The serial mode register 2 (SCSMR2) is an eight-bit register that specifies the SCIF serial
communication format and selects the clock source for the baud rate generator.
The CPU can always read and write the SCSMR2. The SCSMR2 is initialized to H'00 by a reset or
in standby and module standby modes.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
CHR
PE
O/E STOP
—
CKS1 CKS0
0
0
0
0
0
0
0
R/W R/W R/W R/W
R
R/W R/W
Bit 7—Reserved: This bit always read 0. The write value should always be 0.
Bit 6—Character Length (CHR): Selects seven-bit or eight-bit data in the asynchronous mode.
Bit 6: CHR
Description
0
Eight-bit data.
(Initial value)
1
Seven-bit data. *
Note: * When seven-bit data is selected, the MSB (bit 7) of the transmit FIFO data register 2 is not
transmitted.
Bit 5—Parity Enable (PE): Selects whether or not to add a parity bit to transmit data and to
check the parity of receive data.
Bit 5: PE
0
1
Description
Parity bit not added or checked.
(Initial value)
Parity bit added and checked.
When PE is set to 1, an even or odd parity bit is added to transmit data,
depending on the parity mode (O/E) setting. Receive data parity is checked
according to the even/odd (O/E) mode setting.
Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition
and check. The O/E setting is ignored when parity addition and check is disabled.
Rev.6.00 Mar. 27, 2009 Page 572 of 1036
REJ09B0254-0600