HD6417727BP160CV Datasheet, PDF (649/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Transmitting and Receiving Data (SCIF Initialization): Before transmitting or receiving, clear
the TE and RE bits to 0 in the serial control register 2 (SCSCR2), then initialize the SCIF as
follows.
When changing the communication format, always clear the TE and RE bits to 0 before following
the procedure given below. Clearing TE to 0 initializes the transmit shift register 2 (SCTSR2).
Clearing TE and RE to 0, however, does not initialize the serial status register 2 (SCSSR2),
transmit FIFO data register 2 (SCFTDR2), or receive FIFO data register 2 (SCFRDR2), which
retain their previous contents.
Clear TE to 0 after all transmit data are transmitted and the TEND flag in the SCSSR2 is set. The
transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared
to 0 in transmitting. Set the TFRST bit in the SCFCR2 to 1 and reset the SCFTDR2 before TE is
set again to start transmission.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCIF operation becomes unreliable if the clock is stopped.
Rev.6.00 Mar. 27, 2009 Page 591 of 1036
REJ09B0254-0600