HD6417727BP160CV Datasheet, PDF (290/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 8 User Break Controller
4. The change of a UBC register value is executed in MA (memory access) stage. Therefore,
even if the break condition matches in the instruction fetch address following the instruction in
which the pre-execution break is specified as the break condition, no break occurs. In order to
know the timing UBC register is changed, read the last written register. Instructions after then
are valid for the newly written register value.
5. Notes in specifying the instruction during repeat execution with repeat instruction as the break
condition are as follows: When the instruction during repeat execution is specified as the break
condition,
(1) The break is not issued during repeat execution, which has fewer than three instructions.
(2) When the execution times break is set, no instruction fetch from memory occurs during
repeat execution under three instructions. Therefore, the execution times register BETR is
not decreased.
6. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR
are read.
7. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as
follows:
(1) Break and instruction fetch exceptions: Instruction fetch exception occurs first.
(2) Break before execution and operand exception: Break before execution occurs first.
(3) Break after execution and operand exception: Operand exception occurs first.
Rev.6.00 Mar. 27, 2009 Page 232 of 1036
REJ09B0254-0600