HD6417727BP160CV Datasheet, PDF (16/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

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898 30.2.3 Area 6 Card Status Change Register
(PCC0CSCR)
Bit 4—PCC0 Status Change (P0SC):
Bit 4—PCC0 Status Change (P0SC):
Indicates a change in the value of the
Indicates a change in the value of the
STSCHG pin of the PC card when the PC
STSCHG pin of the PC card when the PC card connected to area 6 is the I/O card
card connected to area 6 is the I/O card
interface type. When the STSCHG pin is
interface type. When the STSCHG pin is changed from 1 to 0, the P0SC bit is set to
changed from 1 to 0, the SC bit is set to 1. 1.
922, 31.3.3 Boundary-Scan Register (SDBSR)
923 _{Table 31.3 Correspondence between}
SH7727 Pins and Boundary-Scan Register
Bit
Pin Name
I/O
167
USB1_ovr_crnt /USBF_VBUS IN
166
USB2_ovr_crnt
IN
165
RTS2/USB1d_TXENL
IN
164
PTE2/USB1_PWR_EN
IN
163
PTE1/USB2_PWR_EN
IN
162
CKE/PTK5
IN
161
RAS3/PTJ0
IN
103
RAS3 /PTJ0
Control
Bit
Pin Name
132
PTE1/USB2_PWR_EN
131
CKE/PTK5
130
RAS3/PTJ 0
I/O
OUT
OUT
OUT
Bit
Pin Name
I/O
167
USB1_ovr_current/USBF_VBUS IN
166
USB2_ovr_current
IN
165
RTS2/USB1d_TXENL
IN
164
PTE2/USB1_PWR_EN
IN
163
PTE1/USB2_PWR_EN
IN
162
CKE/PTK5
IN
161
RAS /PTJ0
IN
103
RAS /PTJ0
Control
Bit
Pin Name
132
PTE1/USB2_PWR_EN
131
CKE/PTK5
130
RAS /PTJ0
I/O
OUT
OUT
OUT
933
32.2 DC Characteristics
Table 32.2 DC Characteristics (2)
Item
Input high
voltage
Symbol
RESETP,
VIH
RESETM, NMI,
IRQ5 to IRQ0,
MD5 to MD0,
IRL3 to IRL0,
PINT15 to PINT0,
ASEMD0,
ADTRG, TRST,
EXTAL, CKIO,
CA
EXTAL2
Min
Typ
VCCQ × 0.9 —
—
—
Port L
Other input pins
2.0
—
2.0
—
Max
Unit
VCCQ + 0.3 V
Measurement
Conditions
—
AVCC + 0.3
VCCQ + 0.3
Connect to Vcc when
crystal oscillator is
connected
Item
Input high
voltage
Symbol
RESETP,
VIH
RESETM, NMI,
IRQ5 to IRQ0,
MD5 to MD0,
IRL3 to IRL0,
PINT15 to PINT0,
ASEMD0,
ADTRG, TRST,
EXTAL, CKIO,
CA
EXTAL2
Min
Typ
VCCQ × 0.9 —
—
—
Port L
Other input pins
2.0
—
2.0
—
Max
Unit
VCCQ + 0.3 V
Measurement
Conditions
—
AVCC + 0.3
VCCQ + 0.3
Connect to Vcc-RTC
when no crystal
resonator is
connected
965 32.3.6 Synchronous DRAM Timing
Figure 32.31 Synchronous DRAM Auto-
Refresh Cycle (TRAS = 1, TPC = 1)
RAS3
RAS
966 Figure 32.32 Synchronous DRAM Self-
Refresh Cycle (TPC = 0)
RAS3
RAS
967 Figure 32.33 Synchronous DRAM Mode
Register Write Cycle
CASxx
CAS
Rev.6.00 Mar. 27, 2009 Page xiv of lvi
REJ09B0254-0600