HD6417727BP160CV Datasheet, PDF (196/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 4 Exception Handling
4.2.6 Returning from Exception Handling
The RTE instruction is used to return from exception handling. When RTE is executed, the SPC
value is set in the PC, and the SSR value in SR, and the return from exception handling is
performed by branching to the SPC address.
If the SPC and SSR have been saved in the external memory, set the BL bit in SR to 1, then
restore the SPC and SSR, and issue an RTE instruction.
4.3 Register Description
There are four registers related to exception handling. These are peripheral module registers, and
therefore reside in area P4. They can be accessed by specifying the address in the privileged mode
only.
1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit
exception code. The exception code set in EXPEVT is that for a reset or general exception
event. The exception code is set automatically by hardware when an exception occurs.
EXPEVT can also be modified by software.
2. Interrupt event register 2 (INTEVT2) resides at address H'04000000, and contains a 12-bit
exception code. The exception code set in INTEVT2 is that for an interrupt request. The
exception code is set automatically by hardware when an exception occurs.
3. The interrupt event register (INTEVT) resides at address H'FFFFFFD8, and contains a 12-bit
interrupt exception code or a code indicating the interrupt priority. Which is set when an
interrupt occurs depends on the interrupt source (see tables 7.4 and 7.5). The exception code or
interrupt priority code is set automatically by hardware when an exception occurs. INTEVT
can also be modified by software.
4. The TRAPA exception register (TRA) resides at address H'FFFFFFD0, and contains 8-bit
immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when
a TRAPA instruction is executed. TRA can also be modified by software.
The bit configurations of the EXPEVT, INTEVT, INTEVT2, and TRA registers are shown in
figure 4.3.
Rev.6.00 Mar. 27, 2009 Page 138 of 1036
REJ09B0254-0600