HD6417727BP160CV Datasheet, PDF (194/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 4 Exception Handling
All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction
boundaries. However, an exception is not accepted between a delayed branch instruction and the
delay slot. A re-execution type exception detected in a delay slot is accepted before execution of
the delayed branch instruction. A completion type exception detected in a delayed branch
instruction or delay slot is accepted after execution of the delayed branch instruction. The delay
slot here refers to the next instruction after a delayed unconditional branch instruction, or the next
instruction when a delayed conditional branch instruction is true.
4.2.4 Exception Codes
Table 4.3 lists the exception codes written to bits 11 to 0 of the EXPEVT register (for reset or
general exceptions) or the INTEVT and INTEVT2 registers (for general interrupt requests) to
identify each specific exception event. An additional exception register, the TRAPA (TRA)
register, is used to hold the 8-bit immediate data in an unconditional trap (TRAPA instruction).
Table 4.3 Exception Codes
Exception Type
Reset
General exception events
Exception Event
Power-on reset
Manual reset
H-UDI reset
TLB miss/invalid (read)
TLB miss/invalid (write)
TLB miss/invalid/CPU Address error in
repeat loop
Initial page write
TLB protection violation (read)
TLB protection violation (write)
TLB protection violation in repeat loop
CPU Address error (read)
CPU Address error (write)
Unconditional trap (TRAPA instruction)
Illegal general instruction exception
Illegal slot instruction exception
User breakpoint trap
DMA address error
Exception Code
H'000
H'020
H'000
H'040
H'060
H'070
H'080
H'0A0
H'0C0
H'0D0
H'0E0
H'100
H'160
H'180
H'1A0
H'1E0
H'5C0
Rev.6.00 Mar. 27, 2009 Page 136 of 1036
REJ09B0254-0600