HD6417727BP160CV Datasheet, PDF (767/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 23 USB Function Controller
The application analyzes command data from the host in the setup stage and decides the following
data stage direction. As a result of command data analysis, when the data stage is in-transfer, one-
packet data to be sent to the host is written to FIFO. If there is more data to be sent to the host,
after data written first is sent to the host (USBIFR0/EP0i TS = 1), data is written to FIFO.
The end of the data stage is decided by transferring out-token by the host and entering the status
stage.
Note:
When the size of data transferred from the function is smaller than the size of data
requested from the host, the function indicates data stage end by returning a packet smaller
than the maximum packet to the host. When the size of data transferred from the function
is integer times larger than the maximum packet size, a 0-length packet is transferred and
the data stage end is indicated.
Rev.6.00 Mar. 27, 2009 Page 709 of 1036
REJ09B0254-0600