HD6417727BP160CV Datasheet, PDF(575/1098 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

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HD6417727BP160CV Datasheet, PDF (575/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

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Section 17 Serial Communication Interface (SCI)

1

Serial

data

Start

bit

0 D0

Parity Stop Start

Data bit bit bit

D1

D7 0/1 1 0 D0

Parity Stop

Data bit bit 1

D1

D7

0/1

1 Idle

(marking)

TDRE

TEND

TXI interrupt

request

generated

Writes data to TXI interrupt

SCTDR with the request

TXI interrupt generated

processing routine

and clear TDRE

bit to 0

1 frame

TEI interrupt

request

generated

Figure 17.9 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit)

Rev.6.00 Mar. 27, 2009 Page 517 of 1036

REJ09B0254-0600

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