HD6417727BP160CV Datasheet, PDF (63/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 1 Overview and Pin Functions
Item
Bus state
controller (BSC)
Features
• Physical address space divided into six areas (area 0, areas 2 to 6), each of
up to 64 Mbytes, with the following features settable for each area:
⎯ Bus size (8, 16, or 32 bits)
⎯ Number of wait cycles (hardware wait function also waited)
⎯ Direct connection of SRAM, synchronous DRAM, and burst ROM
possible by designating memory to be connected to each area
⎯ Supports PCMCIA interface (2 channels)
⎯ Chip select signals (CS0, CS2–CS6) for relevant area
• Synchronous DRAM refresh function
⎯ Programmable refresh interval
⎯ Supports CAS-before-RAS refresh and self-refresh modes
⎯ Supports power-down DRAM
• Synchronous DRAM burst access function
• Big endian or little endian can be specified
Li bus state
•
controller (LBSC) _•
•
Bus State Controller for LCDC or USB Host
Supports synchronous DRAM
Synchronous DRAM access function (area 3)
User debug
•
Interface (H-UDI) _•
•
E10A emulator support
Pin arrangement conforming to JTAG specification
Realtime branch trace
Timer (TMU)
• 3-channel auto-reload-type 32-bit timer
• Choice of six counter input clocks
• Maximum resolution: 2 MHz
Realtime clock
(RTC)
• Built-in clock, calendar functions, and alarm functions
• On-chip 32-kHz crystal oscillator circuit with a maximum resolution (cycle
interrupt) of 1/256 second
Serial communi- • Asynchronous mode or clock synchronous mode can be selected
cation interface
(SCI)
• Full-duplex communication
• Supports smart card interface
Rev.6.00 Mar. 27, 2009 Page 5 of 1036
REJ09B0254-0600