HD6417727BP160CV Datasheet, PDF (202/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 4 Exception Handling
⎯ Operations: The logical address (32 bits) that caused the exception is set in TEA. The PC
and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the
exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in
SR are set to 1 and a branch occurs to PC = VBR + H'0100. See section 3.5.5, Processing
Flow in Event of MMU Exception, for more information.
• Unconditional trap
⎯ Conditions: TRAPA instruction executed
⎯ Operations: The exception is a processing-completion type, so the PC of the instruction
after the TRAPA instruction is saved to the SPC. SR from the time when the TRAPA
instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA
instruction is quadrupled and set in TRA (9 to 0). H'160 is set in EXPEVT. The BL, MD,
and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
• Illegal general instruction exception
⎯ Conditions:
a. When undefined code not in a delay slot is decoded
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
Undefined instruction: H'Fxxx
b. When a privileged instruction not in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access
GBR with LDC/STC are not privileged instructions.
c. When a DSP instruction not in a delay slot is decoded without DSP extension
(SR.DSP=0)
DSP instructions: LDS Rm, DSR/A0/X0/X1/Y0/Y1, LDS.L @Rm+,
DSR/A0/X0/X1/Y0/Y1, STS DSR/A0/X0/X1/Y0/Y1, Rn, STS.L
DSR/A0/X0/X1/Y0/Y1, @-Rn, LDC Rm, RS/RE/MOD, LDC.L @Rm+, RS/RE/MOD,
STC RS/RE/MOD, Rn, STC.L RS/RE/MOD, @-Rn, LDRS, LDRE, SETRC, MOVS,
MOVX, MOVY, Pxxx
d. When an instruction that rewrites the PC/SR/RS/RE in the last three instructions of
repeat loop is decoded.
Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE,
BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR,
LDC.L @Rm+, SR
Instructions that rewrite the SR: LDC Rm, SR, LDC.L @Rm+, SR, SETRC
Instructions that rewrite the RS: LDC Rm, RS, LDC.L @Rm+, RS, LDRS
Instructions that rewrite the RE: LDC Rm, RE, LDC.L @Rm+, RE, LDRE
Rev.6.00 Mar. 27, 2009 Page 144 of 1036
REJ09B0254-0600