HD6417727BP160CV Datasheet, PDF (343/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
12.1.2 Block Diagram
Figure 12.1 shows the functional block diagram of the BSC.
MD5 to MD3
WAIT
Mode selection
Wait
controller
WCR1
WCR2
Bus
interface
CS0
CS6 to CS2
CE2A to CE2B
BS
RD
RD/WR
WE3 to WE0
RAS
CAS
CKE
ICIORD, ICIOWR
IOIS16
Interrupt
controller
Legend:
WCR: Wait state contol register
BCR: Bus control register
MCR: Memory control register
PCR: PCMCIS control register
Area
controller
BCR1
BCR2
Memory
controller
Refresh
controller
MCR
PCR
MR2
RFCR
RTCNT
Comparator
RTCOR
RTCSR
BSC
RFCR: Refresh count register
RTCNT: Refresh timer count register
RTCOR: Refresh time constant register
RTCSR: Refresh timer control/status register
Figure 12.1 Corresponding to Logical Address Space and Physical Address Space
Rev.6.00 Mar. 27, 2009 Page 285 of 1036
REJ09B0254-0600