HD6417727BP160CV Datasheet, PDF (265/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 8 User Break Controller
Bits 31 to 0—Break Address Mask Register A31 to A0 (BAMA31 to BAMA0): Specifies bits
masked in the channel A break address bits specified by BARA (BAA31 to BAA0).
Bits 31 to 0:
BAMAn
0
1
Description
Break address bit BAAn of channel A is included in the break condition
(Initial value)
Break address bit BAAn of channel A is masked and is not included in the break
condition
n = 31 to 0
8.2.3 Break Bus Cycle Register A (BBRA)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — CDA1 CDA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the
break conditions of channel A. A power-on reset initializes BBRA to H'0000.
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 7 and 6—CPU Cycle/DMAC Cycle Select A (CDA1, CDA0): Selects the CPU cycle or
DMAC cycle as the bus cycle of the channel A break condition.
Bit 7: CDA1 Bit 6: CDA0
0
0
*
1
1
0
Note: * Don’t care
Description
Condition comparison is not performed
The break condition is the CPU cycle
The break condition is the DMAC cycle
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 207 of 1036
REJ09B0254-0600