HD6417727BP160CV Datasheet, PDF (325/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 10 On-Chip Oscillation Circuits
10.4 Register Descriptions
10.4.1 Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit read/write register that specify the frequency
multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the
peripheral clock.
Only word access can be used on the FRQCR register. FRQCR is initialized to H'0102 by a
power-on reset, but retains its value in a manual reset and in standby mode.
Bit: 15
14
13
12
11
10
9
8
STC2 IFC2 PFC2
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
1
R/W: R/W R/W R/W
R
R
R
R
R
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
—
STC1 STC0 IFC1 IFC0 PFC1 PFC0
0
0
0
0
0
1
0
R
R/W R/W R/W R/W R/W R/W
Bits 15, 5 and 4—Frequency Multiplication Ratio (STC2, STC1, STC0): These bits specify the
frequency multiplication ratio of PLL circuit 1.
Bit 15: STC2 Bit 5: STC1
Bit 4: STC0
Description
0
0
0
×1
(Initial value)
0
0
1
×2
1
0
0
×3
0
1
0
×4
1
0
1
×6
Values other than above
Reserved (illegal setting)
Note: Do not set the output frequency of PLL circuit 1 higher than the maximum frequency of the
CPU specified in AC Characteristics.
Rev.6.00 Mar. 27, 2009 Page 267 of 1036
REJ09B0254-0600