HD6417727BP160CV Datasheet, PDF (431/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 13 Li Bus State Controller (LBSC)
13.1.7 Individual Memory Control Register (MCR)
The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS
and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address
multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without
external circuits.
The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or
standby mode. The bits TPC1 to TPC0, RCD1 to RCD0, TRWL1 to TRWL0, TRAS1 to TRAS0,
and AMX3 to AMX0 are written to at the initialization after a power-on reset and should not be
modified again. When RFSH and RMODE are written to, write the same values to the other bits.
When using synchronous DRAM, do not access areas 2 and 3 until this register initialization is
complete.
Bit:
Initial value:
R/W:
15
TPC1
0
R/W
14
TPC0
0
R/W
13
RCD1
0
R/W
12
RCD0
0
R/W
11
10
9
TRWL1 TRWL0 TRAS1
0
0
0
R/W R/W R/W
8
TRAS0
0
R/W
Bit: 7
—
Initial value: 0
R/W: R/W
6
5
4
3
2
1
0
AMX3 AMX2 AMX1 AMX0 RFSH RMODE ^—
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): When synchronous DRAM interface is
selected, these bits set the minimum number of cycles until output of the next bank-active
command after precharge.
Bit 15: TPC1
0
1
Bit 14: TPC0
0
1
0
1
Description
1 cycle
2 cycles
3 cycles
4 cycles
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 373 of 1036
REJ09B0254-0600