HD6417727BP160CV Datasheet, PDF (823/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 25 LCD Controller
25.1.3 Pin Configuration
Table 25.1 summarizes the LCDC’s pin configuration.
Table 25.1 Pin Configuration
Name
I/O
Function
LCD 15−0
O
Data for LCD panel
DON
O
Display-on signal (DON)
CL1
O
Shift-clock 1 (STN/DSTN)/Horizontal sync signal (HSYNC) (TFT)
CL2
O
Shift-clock 2 (STN/DSTN)/dot clock (DOTCLOCK) (TFT)
M/DISP
O
LCD current-alternation signal/(STN/DSTN),
Display enable BLANK (TFT)/DISP signal
FLM
O
First line marker/Vertical sync signal (VSYNC) (TFT)
VCPWC
O
LCD-module power control (Vcc)
VEPWC
LCLK
O
LCD-module power control (V_EE)
I
LCD clock-source input
Note: Check the LCD module specifications carefully in section 25.4, Clock and LCD Data Signal
Examples, before deciding on the wiring specifications for the LCD module.
25.1.4 Register Configuration
Table 25.2 summarizes the configuration of the LCDC’s registers.
Table 25.2 Register Configuration
Register Name
LCDC input clock register
Abbreviation
LDICKR
LCDC module type register
LDMTR
LCDC data format register
LDDFR
LCDC scan mode register
LDSMR
LCDC data fetch start address register
for upper portion of display panel
LCDC data fetch start address register
for lower portion of display panel
LDSARU
LDSARL
Initial Value
H’0101
H’0109
H’000C
H’0000
H’0C000000
H’0C000000
Address
H’04000C00
(H’A4000C00)*
H’04000C02
(H’A4000C02)*
H’04000C04
(H’A4000C04)*
H’04000C06
(H’A4000C06)*
H’04000C08
(H’A4000C08)*
H’04000C0C
(H’A4000C0C)*
Access Size
16
16
16
16
32
32
Rev.6.00 Mar. 27, 2009 Page 765 of 1036
REJ09B0254-0600