HD6417727BP160CV Datasheet, PDF (10/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

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323 12.3.2 Description of Areas
Area 2:
When synchronous DRAM is connected,
the RAS3 signal, CAS signal, RD/WR
signal, and byte controls DQMHH, DQMHL,
DQMLH, and DQMLL are all asserted and
addresses multiplexed. Control of RAS3,
CAS, data timing, and address multiplexing
is set with MCR.
When synchronous DRAM is connected,
the RAS signal, CAS signal, RD/WR signal,
and byte controls DQMHH, DQMHL,
DQMLH, and DQMLL are all asserted and
addresses multiplexed. Control of RAS,
CAS, data timing, and address multiplexing
is set with MCR.
12.3.2 Description of Areas
Area 3:
When synchronous DRAM is connected,
the RAS3 signal, CAS signal, RD/WR
signal, and byte controls DQMHH, DQMHL,
DQMLH, and DQMLL are all asserted and
addresses multiplexed.
When synchronous DRAM is connected,
the RAS signal, CAS signal, RD/WR signal,
and byte controls DQMHH, DQMHL,
DQMLH, and DQMLL are all asserted and
addresses multiplexed.
331 12.3.4 Synchronous DRAM Interface
RAS3
RAS
332 Figure 12.11 Example of 64-Mbit
Synchronous DRAM Connection (32-Bit
Bus Width)
RAS3
RAS
333 Figure 12.12 Example of 64-Mbit
Synchronous DRAM (16-Bit Bus Width)
RAS3
RAS
336 Figure 12.13 Basic Timing for Synchronous
DRAM Burst Read
RAS3
RAS
337 Figure 12.14 Synchronous DRAM Burst
Read Wait Specification Timing
RAS3
RAS
338 Figure 12.15 Basic Timing for Synchronous
DRAM Single Read
RAS3
RAS
339 Figure 12.16 Basic Timing for Synchronous
DRAM Burst Write
RAS3
RAS
Rev.6.00 Mar. 27, 2009 Page viii of lvi
REJ09B0254-0600