HD6417727BP160CV Datasheet, PDF (279/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 8 User Break Controller
8.2.13 Break ASID Register A (BASRA)
Bit:
Initial value:
R/W:
Note: * Undefined
7
BASA7
*
R/W
6
BASA6
*
R/W
5
BASA5
*
R/W
4
BASA4
*
R/W
3
BASA3
*
R/W
2
BASA2
*
R/W
1
BASA1
*
R/W
0
BASA0
*
R/W
Break ASID register A (BASRA) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel A. It is not initialized by resets. It is located in CCN.
Bits 7 to 0—Break ASID A7 to 0 (BASA7 to BASA0): These bits store the ASID (bits 7 to 0)
that is the channel A break condition.
8.2.14 Break ASID Register B (BASRB)
Bit:
Initial value:
R/W:
Note: * Undefined
7
BASB7
*
R/W
6
BASB6
*
R/W
5
BASB5
*
R/W
4
BASB4
*
R/W
3
BASB3
*
R/W
2
BASB2
*
R/W
1
BASB1
*
R/W
0
BASB0
*
R/W
Break ASID register B (BASRB) is an 8-bit read/write register that specifies the ASID that serves
as the break condition for channel B. It is not initialized by resets. It is located in CCN.
Bits 7 to 0: Break ASID A7 to 0 (BASB7 to BASB0): These bits store the ASID (bits 7 to 0) that
is the channel B break condition.
Rev.6.00 Mar. 27, 2009 Page 221 of 1036
REJ09B0254-0600