HD6417727BP160CV Datasheet, PDF (760/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 23 USB Function Controller
23.5.17 USB Interrupt Select Register 0 (USBISR0)
USBISR0 selects the interrupt event register (INTEVT2) codes of the interrupt requests indicated
in USB interrupt flag register 0. If the USB issues an interrupt request to the INTC when the
corresponding bit in USBISR0 is cleared to 0, the interrupt will be USBFI0 (USB function
interrupt 0), with an interrupt event register (INTEVT2) code of H'A20. If the USB issues an
interrupt request to the INTC when the corresponding bit in USBISR0 is set to 1, the interrupt will
be USBFI1 (USB function interrupt 1), with an interrupt event register (INTEVT2) code of
H'A40. The initial value designates an interrupt event register (INTEVT2) code of H'A20. If
interrupts occur simultaneously, USBFI0 has priority by default. For details on the interrupt event
register (INTEVT2), refer to section 4, Exception Handling, and section 7, Interrupt Controller
(INTC).
Bit:
7
BSRT
Initial value:
0
R/W: R/W
6
EP1
FULL
0
R/W
5
4
3
2
EP2
EP2 SETUP EP0o
TR EMPTY TS
TS
0
0
0
0
R/W
R/W
R/W
R/W
1
EP0i
TR
0
R/W
0
EP0i
TS
0
R/W
23.5.18 USB Interrupt Select Register 1 (USBISR1)
USBISR1 selects the interrupt event register (INTEVT2) codes of the interrupt requests indicated
in USB interrupt flag register 1. If the USB issues an interrupt request to the INTC when the
corresponding bit in USBISR1 is cleared to 0, the interrupt will be USBFI0 (USB function
interrupt 0), with an interrupt event register (INTEVT2) code of H'A20. If the USB issues an
interrupt request to the INTC when the corresponding bit in USBISR1 is set to 1, the interrupt will
be USBFI1 (USB function interrupt 1), with an interrupt event register (INTEVT2) code of
H'A40. The initial value designates an interrupt event register (INTEVT2) code of H'A20. If
interrupts occur simultaneously, USBFI0 has priority by default. For details on the interrupt event
register (INTEVT2), refer to section 4, Exception Handling, and section 7, Interrupt Controller
(INTC).
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
EP3
EP3 VBUS
TR
TS
Initial value:
0
0
0
0
0
1
1
1
R/W: R
R
R
R
R
R/W
R/W
R/W
Rev.6.00 Mar. 27, 2009 Page 702 of 1036
REJ09B0254-0600