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| HD6417727BP160CV Datasheet, PDF (1012/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series | |||
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Section 32 Electrical Characteristics
32.3.5 Burst ROM Timing
T1
TB2
TB1
TB2
TB1
TB2
TB1
T2
CKIO
tAD
A25 to A4
tAD
A3 to A0
tCSD1
CSn
tRWD
RD/WR
tRSD tRSD tAH
RD
tRDH1
tRDS
D31 to D0
tBSD
tBSD
BS
DACKn
tDAKD1
WAIT
tAD
tAD
tAH
tCSD2 tRWH
tRDH1
tRWD
tRSD
tAH
tRSD tRWH
tRDS1
tRDH1
tBSD
tBSD
tDAKD1
tWTS tWTH
Note: In the write cycle, the basic bus cycle is performed.
Figure 32.20 Burst ROM Bus Cycle (No Wait)
Rev.6.00 Mar. 27, 2009 Page 954 of 1036
REJ09B0254-0600
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