HD6417727BP160CV Datasheet, PDF (830/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 25 LCD Controller
Bit 8—Byte Data Pixel Alignment (PABD): Sets the pixel data alignment type in one byte of
data. The contents of aligned data per pixel are the same regardless of this bit's setting. For
example, data H'05 should be expressed as 0101 (binary) which is the normal style handled by a
MOV instruction of the SH7727 CPU, and should not be selected between 0101 (binary) and 1010
(binary).
Bit 8
PABD
0
1
Description
Big endian for byte data
Little endian for byte data
(Initial value)
Bits 6 to 0—Display Color Select (DSPCOLOR6 to DSPCOLOR0): Set the number of display
colors for the display (0 is written to upper bits of for unpacked 4, 5, and 6 bpp). For display
colors to which the description (via palette) is added below, the color set by the color palette is
actually selected by the display data and displayed.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DSP
DSP
DSP
DSP
DSP
DSP
DSP
COLOR6 COLOR5 COLOR4 COLOR3 COLOR2 COLOR1 COLOR0 Description
0
0
0
0
0
0
0
Monochrome, 2 grayscales,
1 bpp (via palette)
1
Monochrome, 4 grayscales,
2 bpp (via palette)
0
1
0
Monochrome, 16 grayscales,
4 bpp (via palette)
1
0
0
Monochrome, 64 grayscales,
6 bpp (via palette)
1
0
1
0
Color, 16 colors, 4 bpp (via
palette)
1
0
0
Color, 256 colors, 8 bpp (via
palette)
1
1
1
0
1
Color, 32k colors (RGB: 555),
15 bpp
1
0
1
1
0
1
Color, 64k colors (RGB: 565),
16 bpp
Other than above
Reserved
Note: The number of colors that can be selected in rotation mode is restricted by the display
resolution. For details, see table 25.3, in section 25.3, Operation.
Rev.6.00 Mar. 27, 2009 Page 772 of 1036
REJ09B0254-0600