HD6417727BP160CV Datasheet, PDF (1038/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 32 Electrical Characteristics
32.3.10 LCDC Timing
Table 32.13 LCDC Timing
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Item
LCLK input clock frequency
LCLK input clock rise time
LCLK input clock fall time
LCLK input clock duty
Clock (CL2/DCLK) cycle time
Clock (CL2/DCLK) high-level width
Clock (CL2/DCLK) low-level width
Clock (CL2/DCLK) transition time
(rise, fall)
Data (LCD) delay time
Data (LCD) transition time (rise, fall)
Display enable (M/DISP) delay time
Display enable (M/DISP) transition
time (rise, fall)
Horizontal sync. signal (CL1/Hsync)
delay time
Horizontal sync. singal (CL1/Hsync)
transition time
Vertical sync. signal (FLM/Vsync)
delay time
Vertical sync. signal (FLM/Vsync)
transition time
Symbol
t_FREQ
t_R
t_F
t_DUTY
t_CC
t_CHW
t_CLW
t_CT
t_DD
t_DT
t_ID
t_IT
t_HD
t_HT
t_VD
t_VT
Min
—
—
—
90
25
7
7
—
–3.5
—
–3.5
—
–3.5
—
–3.5
—
Max
50
3
3
110
—
—
—
3
3
3
3
3
3
3
3
3
Unit
MHz
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
32.51
Rev.6.00 Mar. 27, 2009 Page 980 of 1036
REJ09B0254-0600