HD6417727BP160CV Datasheet, PDF (49/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Figure 32.26 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read × 4),
RCD = 1, CAS Latency = 3, TPC = 0) ................................................................... 960
Figure 32.27 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0).............. 961
Figure 32.28 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1).............. 962
Figure 32.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4),
RCD = 0, TPC = 1, TRWL = 0) ............................................................................. 963
Figure 32.30 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write × 4),
RCD = 1, TPC = 0, TRWL = 0) ............................................................................. 964
Figure 32.31 Synchronous DRAM Auto-Refresh Cycle (TRAS = 1, TPC = 1).......................... 965
Figure 32.32 Synchronous DRAM Self-Refresh Cycle (TPC = 0).............................................. 966
Figure 32.33 Synchronous DRAM Mode Register Write Cycle ................................................. 967
Figure 32.34 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ............................... 968
Figure 32.35 PCMCIA Memory Bus Cycle
(TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) ............................ 969
Figure 32.36 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait)............ 970
Figure 32.37 PCMCIA Memory Bus Cycle
(Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3, WAITSEL = 1) .... 971
Figure 32.38 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)........................................ 972
Figure 32.39 PCMCIA I/O Bus Cycle
(TED = 2, TEH = 1, One Wait, External Wait, WAITSEL = 1) ............................ 973
Figure 32.40 PCMCIA I/O Bus Cycle
(TED = 1, TEH = 1, One Wait, Bus Sizing, WAITSEL = 1) ................................. 974
Figure 32.41 Oscillation Settling Time at RTC Crystal Oscillator Power-on ............................. 976
Figure 32.42 SCK Input Clock Timing ....................................................................................... 976
Figure 32.43 SCI I/O Timing in Clock Synchronous Mode ........................................................ 976
Figure 32.44 I/O Port Timing ...................................................................................................... 977
Figure 32.45 DREQ Input Timing............................................................................................... 977
Figure 32.46 DRAK Output Timing............................................................................................ 977
Figure 32.47 TCK Input Timing.................................................................................................. 978
Figure 32.48 TRST Input Timing (Reset Hold)........................................................................... 979
Figure 32.49 H-UDI Data Transfer Timing................................................................................. 979
Figure 32.50 ASEMD0 Input Timing.......................................................................................... 979
Figure 32.51 LCDC AC Specification......................................................................................... 981
Figure 32.52 SIOMCLK Input Timing........................................................................................ 982
Figure 32.53 SIOF Transmit/Receive Timing (Master Mode 1: Fall Sampling Time) ............... 983
Figure 32.54 SIOF Transmit/Receive Timing (Master Mode 1: Rise Sampling Time)............... 983
Figure 32.55 SIOF Transmit/Receive Timing (Master Mode 2: Fall Sampling Time) ............... 984
Figure 32.56 SIOF Transmit/Receive Timing (Master Mode 2: Rise Sampling Time)............... 984
Figure 32.57 SIOF Transmit/Receive Timing (Slave Mode 1 and Slave Mode 2)...................... 985
Figure 32.58 USB Clock Timing................................................................................................. 985
Figure 32.59 AFEIF Module AC Timing .................................................................................... 988
Rev.6.00 Mar. 27, 2009 Page xlvii of lvi
REJ09B0254-0600