HD6417727BP160CV Datasheet, PDF (912/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 27 I/O Ports
27.8 Port L
27.8.1 Port L Data Register (PLDR)
Bit: 7
6
5
4
3
2
1
0
PL7DT PL6DT PL5DT PL4DT PL3DT PL2DT —
—
Initial value: *
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
Note: * Undefined
Port L Data Register (PLDR) is an 8-bit read register that stores data for pins PTL7 to PTL2.
PL7DT to PL2DT bit corresponds to PTL7 to PTL2 pin. When the pin function is general input
port, if the port is read, the corresponding pin level is read. Table 27.7 shows the function of
PLDR.
PLDR is initialized to a power-on reset. It retains its previous value in software standby mode and
sleep mode, and by a manual reset.
Table 27.7 Read/Write Operation of the Port L Data Register (PLDR)
PLnMD1 PLnMD0 Pin State
Read
Write
0
0
Other function H'00
1
Reserved^*1 ⎯
Ignored (no affect on pin state)
⎯
1
*
Input
Pin state
Ignored (no affect on pin state)
Notes: * Undefined
1. Operation cannot be guaranteed when this bit it set to “reserved.”
(n = 2 to 7)
Rev.6.00 Mar. 27, 2009 Page 854 of 1036
REJ09B0254-0600