HD6417727BP160CV Datasheet, PDF (296/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 9 Power-Down Modes and Software Reset
Bit 6—MD5 to MD0 Pin Control (MDCHG): Specifies whether or not pins MD5 to MD0 are
switched in standby mode. When this bit is set to 1, the MD5 to MD0 pin values are latched when
returning from standby mode by means of a reset or interrupt.
Bit 6: MDCHG
0
1
Description
Pins MD5 to MD0 are not switched in standby mode
Pins MD5 to MD0 are switched in standby mode
(Initial value)
Bit 5— Module Stop 8 (MSTP8): Specifies halting the clock supply to the user break controller
(UBC) in the on-chip supporting module. When the MSTP8 bit is set to 1, the clock supply to the
UBC is halted.
Bit 5: MSTP8
0
1
Description
UBC runs
Clock supply to UBC is halted
(Initial value)
Bit 4—Module Stop 7 (MSTP7): Specifies halting of clock supply to the direct memory access
controller (DMAC) in the on-chip supporting module. When the MSTP7 bit is set to 1, the clock
supply to the DMAC is halted.
Bit 4: MSTP7
0
1
Description
DMAC runs
Clock supply to DMAC halted
(Initial value)
Bit 3—Module Stop 6 (MSTP6): Specifies halting of clock supply to the D/A converter (DAC)
in the on-chip supporting module. When the MSTP6 bit is set to 1, the clock supply to the DAC is
halted.
Bit 3: MSTP6
0
1
Description
DAC runs
Clock supply to DAC halted
(Initial value)
Bit 2—Module Stop 5 (MSTP5): Specifies halting of clock supply to the A/D converter (ADC)
in the on-chip supporting module. When the MSTP5 bit is set to 1, the clock supply to the ADC is
halted and all registers are initialized.
Rev.6.00 Mar. 27, 2009 Page 238 of 1036
REJ09B0254-0600