HD6417727BP160CV Datasheet, PDF (559/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 17 Serial Communication Interface (SCI)
The bit rate register (SCBRR) is an eight-bit register that, together with the baud rate generator
clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR),
determines the serial transmit/receive bit rate.
The CPU can always read and write the SCBRR.
The SCBRR is initialized to H'FF by a reset or in module standby or standby mode. Each channel
has independent baud rate generator control, so different values can be set in two channels.
The SCBRR setting is calculated as follows:
Asynchronous mode: N =
Pφ
× 10⁶ – 1
64 × 2^2n–1 × B
Clock synchronous mode: N =
Pφ
× 10⁶ – 1
8 × 2^2n–1 × B
B: Bit rate (bit/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 17.3.)
Table 17.3 SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
Note: Find the bit rate error for the asynchronous mode by the following formula:
Error (%) =
Pφ × 10⁶
(N + 1) × B × 64 × 2^2n–1
– 1 × 100
Table 17.4 lists examples of SCBRR settings in the asynchronous mode; table 17.5 lists examples
of SCBRR settings in the clock synchronous mode.
Rev.6.00 Mar. 27, 2009 Page 501 of 1036
REJ09B0254-0600