HD6417727BP160CV Datasheet, PDF (721/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
Bit 0—Relay Control (RLYC): The signal controls Hook Relay.
Bit 0: RLYC
0
1
Description
On hook state. AFE_RLYCNT goes Low Level.
Off hook state. AFE_RLYCNT goes High Level.
(Initial value)
21.2.2 Make Ratio Count Register (MRCR)
MRCR is the counter that specifies make ratio of dial pulse. Make interval is specified with
AFE_FS as base clock of 9,600 Hz.
Pulse signal is not output when an invalid data (a data that is greater than 1E0H in case of PPS = 1
(20 pps), or a data that is greater than 3C0H in case of PPS = 0 (10 pps)) was input.
Bit: 15 14 13 12 11 10
——————
Initial value: 0 0 0 0 0 0
R/W: R R R R R R
9 to 0
MRCR
0
R/W
21.2.3 Minimum Pause Count Register (MPCR)
MPCR is a counter that sets the dial number interval of the dial pulse. The interval is specified
with AFE_FS as base clock of 9600 Hz.
Bit:
Initial value:
R/W:
15 to 0
MPCR
0
R/W
Rev.6.00 Mar. 27, 2009 Page 663 of 1036
REJ09B0254-0600