HD6417727BP160CV Datasheet, PDF (447/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bit 17—Acknowledge Mode (AM): AM specifies whether DACK is output in data read cycle or
in data write cycle in dual address mode.
In single address mode, DACK is always output regardless of this bit specification.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Bit 17: AM
0
1
Description
DACK output in read cycle
DACK output in write cycle
(Initial value)
Bit 16—Acknowledge Level (AL): AL specifies the DACK (acknowledge) signal output is high
active or low active.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Bit 16: AL
0
1
Description
Low-active output of DACK
High-active output of DACK
(Initial value)
Bits 15 and 14—Destination Address Mode 1, 0 (DM1 and DM0): DM1 and DM0 select
whether the DMA destination address is incremented, decremented, or fixed.
Bit 15: DM1 Bit 14: DM0 Description
0
0
Fixed destination address*
(Initial value)
1
Destination address is incremented (+1 in 8-bit transfer, +2 in
16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer)
1
0
Destination address is decremented (–1 in 8-bit transfer, –2 in
16-bit transfer, –4 in 32-bit transfer; illegal setting in 16-byte
transfer)
1
Reserved (illegal setting)
Note: * This setting cannot be used to perform 16-byte transfers with a destination in X/Y memory.
Rev.6.00 Mar. 27, 2009 Page 389 of 1036
REJ09B0254-0600