HD6417727BP160CV Datasheet, PDF (813/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 24 USB HOST Module
Register: HcRhPortStatus[1:2]
Bits
Reset R/W
3
0
R/W
2
0
R/W
Offset: 54–57, 58–5B
Description
(read) PortOverCurrentIndicator (POCI)
This bit is valid only when a root hub is placed in such a way
that an over-current condition is reported on the base of each
port. If the over-current report at each port is not supported, this
bit is set to 0. If this bit is cleared, all power controls are normal
in this port. If this bit is set, an over-current status exists in this
port. This bit always reflects an over-current input signal.
0 = No over-current condition (initial value)
1 = Over-current condition is detected
(write) ClearSuspendStatus
Writing a 1 initiates a resume. Writing a 0 has no effect. If
PortSuspendStatus is set, a resume is initiated.
(read) PortSuspendStatus (PSS)
This bit indicates that the port is suspended or during the
resume sequence. Writing SetSuspendState sets this bit and
setting PortSuspendStatusChange clears this bit at the end of
the resume interval. If CurrentConnectStatus is cleared, this bit
cannot be set. When portResetStatusChange is set upon
completion of the port reset or HC is placed in the UsbResume
state, this bit is cleared. If an upstream resume is in progress, it
is transmitted to the host controller.
0 = Port is not suspended
1 = Port is selectively suspended
(write) SetPortSuspend
Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect.
In addition, when CurrentConnectStatus is cleared,
PortSuspendStatus is not set by this writing. Instead,
ConnectStatusChange is set. This reports the suspended state
of the power disconnection to the driver.
Rev.6.00 Mar. 27, 2009 Page 755 of 1036
REJ09B0254-0600