HD6417727BP160CV Datasheet, PDF (193/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 4 Exception Handling
Pipeline Sequence:
Instruction n
IF
Instruction n + 1
Instruction n + 2
Detection Order:
ID EX MA WB
TLB miss (data access)
IF ID EX MA WB
TLB miss (instruction access)
IF ID EX MA WB
RIE (reserved instruction exception)
TLB miss (instruction n+1)
TLB miss (instruction n) and RIE (instruction n + 2) = simultaneous detection
Handling Order:
Program Order:
TLB miss (instruction n)
1
Re-execution of instruction n
TLB miss (instruction n + 1)
2
Re-execution of instruction n + 1
RIE (instruction n + 2)
3
IF = Instruction fetch
ID = Instruction decode
EX = Instruction execution
MA = Memory access
WB = Write back
Figure 4.2 Example of Acceptance Order of General Exceptions
Rev.6.00 Mar. 27, 2009 Page 135 of 1036
REJ09B0254-0600